Japanese patent application no. 11-263279, filed Sep. 17, 1999, is hereby incorporated by reference in its entirety.
Embodiments include semiconductor devices including a non-volatile memory transistor with a split gate structure, and methods for manufacturing the same.
In recent years, a mixed-mounting of various circuits is utilized in view of various demands such as a shortened chip-interface delay, a lowered cost per circuit board, a lowered cost in design and development of a circuit board and the like. A mixed-mounting technology for mounting memory and logic has become one of the important technologies. However, such a mixed-mounting technology presents problems that result in complex processes and higher costs for manufacturing ICs.
One embodiment of the present invention relates to a method for manufacturing a semiconductor device including a non-volatile memory transistor having a split gate structure formed in a memory region and a capacitor formed in a capacitor region, the capacitor having a structure in which a capacitor insulation layer is interposed between a first capacitor electrode and a second electrode, the method including the steps of (a) forming the first capacitor electrode in the capacitor region; (b) forming the capacitor insulation layer in the capacitor region; (c) forming a gate insulation layer that becomes a component of the non-volatile memory transistor in the memory region; (d) forming a floating gate that becomes a component of the non-volatile memory transistor in the memory region; (e) forming an intermediate insulation layer that becomes a component of the non-volatile memory transistor in the memory region; (f) forming a control gate that becomes a component of the non-volatile memory transistor in the memory region; and (g) forming the second capacitor electrode in the capacitor region. The step (a) and the step (d) are different steps, and the step (f) and the step (g) are a common step.
Another embodiment relates to a semiconductor device including a non-volatile memory transistor having a split gate structure, the semiconductor device including a capacitor having a structure in which a capacitor insulation layer is placed between a first capacitor electrode and a second capacitor electrode, wherein a floating gate that is a component of the non-volatile memory transistor has a film thickness that is different from that of the first capacitor electrode.
Another embodiment relates to a semiconductor device including a non-volatile memory transistor having a split gate structure, the semiconductor device including a capacitor having a structure in which a capacitor insulation layer is interposed between a first capacitor electrode and a second capacitor electrode, wherein a floating gate that is a component of the non-volatile memory transistor has an impurity concentration that is different from that of the first capacitor electrode.
Another embodiment relates to a semiconductor device including a non-volatile memory transistor having a split gate structure, the semiconductor device including a capacitor having a structure in which a capacitor insulation layer is interposed between a first capacitor electrode and a second capacitor electrode, wherein a floating gate that is a component of the non-volatile memory transistor is formed from a material that is different from that of the first capacitor electrode.
Another embodiment relates to a method for manufacturing a semiconductor device including a non-volatile memory transistor having a split gate structure formed in a memory region and a capacitor formed in a capacitor region, the capacitor including a capacitor insulation region positioned between a first capacitor electrode and a second capacitor electrode, the method including forming the first capacitor electrode in the capacitor region. The capacitor insulation layer is formed in the capacitor region. A gate insulation layer that becomes a component of the non-volatile memory transistor is formed in the memory region. A floating gate that becomes a component of the non-volatile memory transistor is formed in the memory region. An intermediate insulation layer that becomes a component of the non-volatile memory transistor is formed in the memory region. A control gate that becomes a component of the non-volatile memory transistor is formed in the memory region. The second capacitor electrode is formed in the capacitor region. The control gate and the second capacitor electrode are formed from the same material during the same processing step.